2.1 IBM Power10 processor
Figure 2-1 shows the logical system architecture of the Power E1080 server.
Figure 2-1 Power E1080 logical system
The IBM Power10 processor was introduced to the general public on August 17, 2020 at the 32nd HOT CHIPS1 semiconductor conference. At that meeting, the new capabilities and
features of the latest Power processor microarchitecture and the Power Instruction Set Architecture (ISA) v3.1B were revealed and categorized according to the following Power10 processor design priority focus areas:
Ê Data plane bandwidth focus area
Terabyte per second signaling bandwidth on processor functional interfaces, petabyte system memory capacities, 16-socket symmetric multiprocessing (SMP) scalability, and memory clustering and memory inception capability.
Ê Powerful enterprise core focus area
New core micro-architecture, flexibility, larger caches, and reduced latencies.
Ê End-to-end security focus area
Hardware enabled security features that are co-optimized with PowerVM hypervisor support.
Ê Energy efficiency focus area Up to threefold energy efficiency improvement in comparison to POWER9 processor technology.
1 https://hotchips.org/
50 IBM Power E1080: Technical Overview and Introduction
Ê Artificial intelligence (AI)-infused core focus area
A 10-20x matrix-math performance improvement per socket compared to the POWER9 processor technology capability.
The remainder of this section provides more specific information about the Power10 processor technology as it is used in the Power E1080 scale-up enterprise class server.
The IBM’s Power10 Processor session material as presented at the 32nd HOT CHIPS conference is available through the HC32 conference proceedings archive at this web page.